d.
e.
f.
g.
h.
i.
j.
k.
Select R1 component value such that 50k ? ≤ R1 ≤ 100k ?
Calculate R2 base on the desired Vout
R2 = R1 / [(Vout / 0.80V) – 1]
Select the ratio of Rz2 / R1 gain for the desired gain bandwidth
Rz2 = (R1) (Vramp_pp / Vin_max) (fco / fp_LC)
Calculate Cz2 by placing the zero at ? of the output filter pole frequency
Cz2 = 1 / π (Rz2) (fp_LC)
Calculate Cp1 by placing the first pole at ESR zero frequency
Cp1 = 1 / 2 π (Rz2) (fz_ESR)
Calculate Rz3 by setting the second pole at ? of the switching frequency and the
second zero at the output filter double pole frequency
Rz3 = 2 (R1) (fp_LC) / fs
Calculate Cz3 from Rz3 component value above
Cz3 = 1 / π (Rz3) (fs)
Choose 100pF ≤ Cf1 ≤ 220pF to stabilize the SP6134CU internal Error Amplify
As a particular example, consider for the following SP6134EB with a type III Voltage
Loop Compensation component selections:
Vin_max = 15V
Vout = 3.30V @ 0 to 2A load
Select L = 4.7uH => yield ≈ 45% of maximum 2A output current ripple.
Select Cout = 22uF Ceramic capacitors (Resr ≈ 2m ? )
fs = 600khz SP6134CU internal Oscillator Frequency
Vramp_pp = 1.0V SP6134CU internal Ramp Peak to Peak Amplitude
Step by step design procedures :
a.
b.
c.
d.
e.
f.
g.
h.
fco = 600khz / 10 = 60khz
fp_LC = 1 / 2 π [(4.7uH)(22uF)]^1/2 ? 16khz
fz_ESR = 1 / 2 π (2m ? )(22uF) ≈ 3.6Mhz
R1 = 68.1k ? , 1%
R2 = 68.1k ? / [(3.30V / 0.80V) – 1] ? 21.5k ? , 1%
Rz2 = 68.1k ? (1.0V / 15V) (60khz / 16khz) ≈ 20.0k ? , 1%
Cz2 = 1 / π (20.0k ? ) (16khz) ≈ 1,000pF, COG
Cp1 = 1 / 2 π (20.0k ? ) (3.6Mhz) ≈ 2pF => Cp1 = 22pF, COG for noise filtering
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